逻辑晶体管以及非易失性存储器单元集成

Logic transistor and non-volatile memory cell integration

Abstract

The invention relates to a logic transistor and non-volatile memory cell integration. A first conductive layer (30) and an underlying charge storage layer (20) are patterned to form a control gate (32) in an NVM region (12). A first dielectric layer (34) and barrier layer (35) are formed over the control gate. A sacrificial layer (36) is formed over the barrier layer and planarized. A first patterned masking layer (38) in the NVM region defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer (38) defines a logic gate location in the logic region (14). Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location and a second portion remains at the logic gate location. A second dielectric layer (52) is formed over, and planarized to expose, the first and second portions. The first and second portions are removed to result in openings at the select gate location and at the logic gate location which expose the barrier layer.
本发明涉及逻辑晶体管以及非易失性存储器单元集成。第一导电层(30)和下面的电荷存储层(20)被图案化以在NVM区域(12)内形成控制栅极(32)。第一介电层(34)和阻挡层(35)形成于所述控制栅极之上。牺牲层(36)形成于所述阻挡层之上并且被平面化。第一图案化的掩膜层(38)形成于所述NVM区域内的所述牺牲层和控制栅极之上并且定义了与所述控制栅极横向相邻的选择栅极位置。第二掩膜层(38)形成于定义了逻辑栅极位置的逻辑区域(14)内。所述牺牲层的暴露部分被移除以便第一部分保留在所述选择栅极位置处。第二介电层(52)形成于所述第一部分之上并且被平面化以暴露所述第一部分。所述第一部分被移除以在暴露所述阻挡层的所述选择栅极位置处引起开口。

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    CN-105097693-ANovember 25, 2015中芯国际集成电路制造(上海)有限公司Semiconductor device and manufacture method thereof, and electronic device