Semiconductor memory

  • Inventors: MATSUOKA KOJI
  • Assignees: Nec Corp
  • Publication Date: December 15, 1992
  • Publication Number: JP-H04362595-A


PURPOSE: To eliminate precharging time in appearance, to shorten cycle time and to increase data throughput. CONSTITUTION: A bit line controller 2 and a word line controller 3 are connected to a memory plane 1, and they are controlled by an interleaving controller 5. The memory cell of the memory plane 1 is provided with two systems of a bit line 9 and they are used alternatively. Thus, succeeding memory access is performed without waiting the finish of precharging operation making the bit line 9 a readable state. COPYRIGHT: (C)1992,JPO&Japio




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    JP-2006278778-AOctober 12, 2006Nec Electronics Corp, Necエレクトロニクス株式会社半導体装置
    JP-2011501340-AJanuary 06, 2011エス. アクア セミコンダクター, エルエルシー2つのゲート用トランジスタを有する多値メモリ記憶装置